Interconnect Delay Minimization Using a Novel Pre-Mid-Post Buffer Strategy
نویسندگان
چکیده
We consider the problem of minimizing the delay in transporting a signal across a distance in a VLSI circuit.The problem can be restated as a combined buffer insertion, buffer sizing and wire sizing problem. We propose a simple buffering architecture for this problem and show that this architecture achieves a near optimal solution. We also derive simple models for a buffered wire which are suitable for high level design.
منابع مشابه
Buffer Insertion for Delay Minimization using An Improved PSO Algorithm
This paper considers the problem of interconnect wire delay in digital integrated circuits. The correct wire sizing and buffer insertion/sizing can reduce the interconnect delay. The interconnect wire is divided into segments and to optionally buffers are inserted between two adjacent segments. But it is important to select appropriate values for the size of buffers as well as the lengths and w...
متن کاملPerformance optimization of VLSI interconnect layout
This paper presents a comprehensive survey of existing techniques for interconnect optimizationduring the VLSI physical design process, with emphasis on recent studies on interconnect design and optimization for high-performance VLSI circuit design under the deep submicron fabrication technologies. First, we present a number of interconnect delay models and driver/gate delay models of various d...
متن کاملAn optimized buffer insertion algorithm with delay-power constraints for VLSI layouts
We propose a grid-graph algorithm for interconnect routing and buffer insertion in nanometer VLSI layout designs. The algorithm is designed to handle multiconstraint optimizations, namely timing performance and power dissipation. The proposed algorithm is called HRTB-LA, which stands for hybrid routing tree and buffer insertion with look-ahead. In recent VLSI designs, interconnect delay has bec...
متن کاملFast interconnect optimization
Fast Interconnect Optimization. (December 2005) Zhuo Li, B.E., Xi’an JiaoTong University; M.S., Xi’an JiaoTong University Chair of Advisory Committee: Dr. Weiping Shi As the continuous trend of Very Large Scale Integration (VLSI) circuits technology scaling and frequency increases, delay optimization techniques for interconnect are increasingly important for achieving timing closure of high per...
متن کاملAn efficient and optimal algorithm for simultaneous buffer and wire sizing
In this paper, we consider the problem of interconnect delay minimization by simultaneous buffer and wire sizing under the Elmore delay model. We first present a polynomial time algorithm SBWS to minimize the delay of an interconnect wire. Previously, no polynomial time algorithm for the problem has been reported in the literature. SBWS is an iterative algorithm with guaranteed convergence to t...
متن کامل